1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the invention relates to a configuration of an input circuit adaptable to multiple types of interfaces. More specifically, the invention relates to a configuration of an input circuit of a synchronous semiconductor device operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 18 schematically shows an exemplary configuration of a conventional input circuit. Referring to FIG. 18, input circuit 902 includes a comparison circuit 902a for comparing an externally supplied signal EXSI with a reference voltage VREF to generate a signal according to a result of comparison, and an inverter 902b buffering (amplifying) the output signal from comparison circuit 902a to generate internal signal INSI. Comparison circuit 902a and inverter 902b receive internal power supply voltage VDDP as an operating power supply voltage.
Reference voltage VREF is generated by a reference voltage generation circuit 900. Reference voltage generation circuit 900 includes a constant current source 900a, connected to an external power supply node which receives external power supply voltage EXVDD, for generating a constant current of a constant magnitude, and a current/voltage converting element (Z) 900b converting the constant current supplied from constant current source 900a into a voltage to generate reference voltage VREF on a node 900c. Current/voltage converting element 900b is constituted of a resistance element or a MOS transistor (insulated gate field effect transistor) having a gate and a drain connected together, for example.
FIG. 19 is a signal waveform diagram representing an operation of the input circuit shown in FIG. 18. The operation of the input circuit shown in FIG. 18 is now described briefly with reference to FIG. 19.
Comparison circuit 902a has a negative input receiving external signal EXSI and a positive input receiving reference voltage VREF to function as a differential amplifier circuit.
When external signal EXSI is higher than reference voltage VREF, the output signal from comparison circuit 902a is at a low level according to the difference in between. Inverter 902b amplifies and inverts the low level signal from comparison circuit 902a to output the resultant signal, and thus internal signal INSI attains a logical high level (hereinafter H level) at the level of internal power supply voltage VDDP.
When external signal EXSI is lower than reference voltage VREF, comparison circuit 902a outputs a high level signal according to the difference in between. Inverter 902b inverts and amplifies the output signal from comparison circuit 902a, and thus internal signal INSI attains a logical low level (hereinafter L level) at the ground voltage level.
In this way, internal signal INSI has its logic level quickly changeable each time external signal EXSI crosses reference voltage VREF. Thus, the internal signal having a waveform with sharp rising/falling can be generated. In other words, with this differential amplifier circuit 902a, external signal EXSI is compared with reference voltage VREF to generate internal signal INSI according to a result of comparison, so that an internal signal having a sharp rising/falling can be generated even if external signal EXSI is distorted in waveform.
Reference voltage VREF is set to a voltage level according to the amplitude of the external signal, or the intermediate level of the amplitude of external signal EXSI. For example, if external signal EXSI is 1.8 V (=VDDQ), reference voltage VREF is set at 0.9 V.
FIG. 20 schematically shows a relation between the logical high level (H level) and the logical low level (L level) of external signal EXSI and the reference voltage. Referring to FIG. 20, the lower limit of H level of external signal EXSI is the level of voltage VIH while the upper limit of L level thereof is the level of voltage VIL. In general, for an LVTTL (Low Voltage Transistor Transistor Logic) interface, the lower limit voltage of H level, VIH, is set at 2.0 V, and the upper limit voltage of L level, VIL, is set at 0.8 V. Accordingly, for this LVTTL interface, reference voltage VREF is set at the intermediate value in between, i.e., 1.4 V.
However, for a recent 1.8 V interface used for transferring signal/data by means of an output circuit of a low power supply voltage, the H level lower limit voltage VIH is set at the voltage level of 0.8xc2x7VDDQ and the L level upper limit voltage VIL is set at the voltage level of 0.2xc2x7VDDQ, where VDDQ represents an operating power supply voltage of a circuit driving the external signal EXSI. In this case, reference voltage VREF has its voltage level set at the intermediate value, i.e., 0.9 V.
Referring back to FIG. 18, reference voltage VREF is generated through conversion of the constant current from constant current source 900a into voltage by current/voltage converting element 900b. Reference voltage VREF thus has a constant voltage level which is independent of voltage VDDQ. Power supply voltage VDDQ is allowed to vary within the range from 1.65 V to 1.95 V in the specification value.
Referring to FIG. 21A, when power supply voltage VDDQ increases to 1.95 V, H level lower limit voltage VIH of external signal EXSI attains 1.56 V while L level upper limit voltage VIL thereof attains 0.36 V. Reference voltage VREF is constant at 0.9 V, so that the difference between reference voltage VREF and H level lower limit voltage VIH is 0.66 V while the difference between reference voltage VREF and L level upper limit voltage VIL is 0.54 V. Accordingly, there is a difference between the time required for external signal EXSI of H level to change toward L level to cross reference voltage VREF and the time required for external signal EXSI of L level to change toward H level to cross reference voltage VREF. Consequently, the response of the internal signal to the falling of the external signal is delayed.
Referring to FIG. 21B, when power supply voltage VDDQ decreases to 1.65 V, H level lower limit voltage VIH attains 1.32 V while L level upper limit voltage VIL transitions to 0.32 V. Reference voltage VREF is also 0.9 V, and thus the difference between H level lower limit voltage VIH and reference voltage VREF is 0.42 V while the difference between reference voltage VREF and L level upper limit voltage VIL is 0.58 V. Consequently, the response of the internal signal to rising of the external signal is delayed.
Specifically, as shown with some exaggeration in FIG. 22A, when power supply voltage VDDQ increases, the response of internal signal INSI to the falling of external signal EXSI is delayed and the response thereof to the rising of external signal EXSI is advanced. Thus, the period during which internal signal INSI is at H level is shorter than that of an ideal response waveform indicated by the dotted line in FIG. 22A.
In contrast, as shown in FIG. 22B, when the power supply voltage VDDQ decreases, the level of reference voltage VREF relatively increases. Then, the response of internal signal INSI to the falling of external signal EXSI is advanced while the response thereof to the rising of external signal EXSI is delayed. Consequently, the period of H level of internal signal INSI is longer than that of an ideal response waveform indicated by the dotted line in FIG. 22B.
In other words, the variation in the level of power supply voltage VDDQ which defines H level of external signal EXSI causes delay in the rising or falling response of internal signal INSI, resulting in a problem that an internal signal responding accurately to change of an external signal cannot be generated.
It is considered that external signal EXSI changes between H level lower limit voltage VIH and L level upper limit voltage VIL due to a propagation loss of a signal transmission line. Then, the difference between H level lower limit voltage VIH and reference voltage VREF would become different from that between L level upper limit voltage VIL reference voltage when external power supply voltage VDDQ varies. In this case, an input circuit has different operating margins for the H level and LOW level voltages, respectively. Consequently, a sufficient operating margin cannot be ensured and a problem arises accordingly that an internal signal corresponding accurately to an external signal cannot be generated.
In particular, power supply voltage VDDQ is used for an operating power supply voltage of a signal/data output circuit. Therefore, if the operating power supply voltage of an output circuit on the transmission side varies in outputting of a signal/data, there is caused an increased variation in the voltage level of the input signal of a semiconductor memory device on the reception side. Consequently, there arises a problem that it is difficult to accurately determine the logic level of an input signal to generate an internal signal according to the input signal.
Depending on processing systems, there may be a case where different interfaces are used. Such systems include a system transferring signal/data in accordance with an LVTTL interface and a system transferring signal/data in accordance with a 1.8 V system interface as described above. If chips are separately and individually designed for such plurality of interfaces, the design efficiency would deteriorate. Therefore, in general, a common chip design is employed for a plurality of interfaces and the level of the reference voltage is finally set according to an interface to be practically employed.
Even when such a plurality of interfaces include an interface receiving an input signal which has an H level lower limit voltage and an L level upper limit voltage that depend on a power supply voltage level as described above, it is still required to determine the logic level of the input signal accurately regardless of variations of the power supply voltage without affecting an processing speed of an internal signal.
An object of the present invention is to provide an input circuit capable of generating an internal signal in accurate and stable manner even if a power supply voltage which defines the amplitude of an external signal varies.
Another object of the invention is to provide an input circuit readily adaptable to a plurality of types of interfaces and capable of accurately determining the logic level of an input signal without deterioration in signal processing speed.
A semiconductor device according to a first aspect of the present invention includes a reference voltage generation circuit generating a reference voltage, from a first power supply voltage supplied from a first power supply pad, depending on the first power supply voltage, a first input circuit receiving a first input signal and determining a logic level of the first input signal according to a relation between the voltage levels of the reference voltage and the first input signal to generate a first internal signal at a level of a second power supply voltage different from the first power supply voltage according to a result of determination, and an output circuit receiving, from a second power supply pad provided separately from the first power supply pad, the first power supply voltage as an operating power supply voltage to buffer a received signal for external output.
A semiconductor device according to a second aspect of the present invention includes a gate circuit receiving a first power supply voltage as an operating power supply voltage for buffering an input signal and generating an output signal having an amplitude corresponding to a level of the first power supply voltage, and a level conversion circuit for converting the output signal generated by the gate circuit into a signal having an amplitude corresponding to a level of the second power supply voltage to generate an internal signal. The input signal has its logic level determined by a voltage depending on a second power supply voltage.
A semiconductor device according to a third aspect of the present invention includes a first clock input circuit receiving a first power supply voltage as an operating power supply voltage, and comparing an externally supplied external clock signal with a first reference voltage and generating an internal clock signal corresponding to the external clock signal according to a result of the comparison when activated, a second clock input circuit receiving a second power supply voltage as an operating power supply voltage, and comparing the external clock signal with a second reference voltage and generating a second internal clock signal corresponding to the external clock signal according to a result of the comparison, a first clock control circuit for generating a first clock control signal to activate the first clock input circuit in accordance with the clock signal and a clock enable signal instructing whether the clock signal is valid or invalid, and a second clock control circuit for generating a second clock control signal to activate the second clock input circuit in accordance with the external clock signal and the clock enable signal.
The logic level of the first input signal is determined according to a relation between the voltage levels of the reference voltage depending on the first power supply voltage and the first input signal. Even if the level of the first power supply voltage varies, the internal signal can accurately be generated regardless of the variation of the first power supply voltage level, since the logic level of the input signal is determined based on the first power supply voltage.
With respect to clock signals, a plurality of circuit systems are provided according to available levels of the power supply voltage. According to a level of the power supply voltage, a corresponding clock signal generation circuit system is activated. Even if the external power supply voltage is changed to accompany a change in the amplitude of the clock signal, an internal clock signal can accurately and readily be generated according to the external clock signal.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.